1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of forming a semiconductor device having a low resistance gate electrode.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. By way of background, FIG. 1 depicts an illustrative NMOS field effect transistor 10 formed above a surface 14 of a semiconducting substrate 12 between trench isolation regions 25. The transistor 10 is comprised of a gate dielectric 16, a gate electrode 18, a plurality of sidewall spacers 20 and multiple source/drain regions 28. The transistor 10 is further comprised of metal silicide contacts 21 formed on the source/drain regions 28 and on the gate electrode 18. These metal silicide contacts 21 are typically relatively thin, e.g., on the order of 200-300 xc3x85.
The aforementioned demand for increased operating speed of integrated circuit devices has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, the size of many components of a typical field effect transistor, e.g., channel length, source/drain junction depths, gate dielectric thickness, etc., are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. However, some metal suicides, like titanium silicide, do not scale very well. That is, as linewidths are reduced, the resistance can increase rapidly.
As the channel length has been reduced to obtain the desired switching characteristic, the length (in the transverse direction) of the gate electrode 18 has also been reduced. Since the gate electrode 18 may only be electrically connected at one end, the electrical charges used to establish a transverse electrical field for forming the channel between the source/drain regions 28 of the transistor 10 have to be transported along the entire width (in the longitudinal direction) of the gate electrode, i.e., along the direction into the drawing page of FIG. 1. Given the small length of the gate electrode 18, the electrical resistance is relatively high, which may result in higher RC-delay time-constants. Hence, generation of the transverse electrical field used to fully open the channel is delayed, thereby deteriorating the switching time of the transistor. As a consequence, the rise and fall times of the electrical signals are increased and the operating frequency, i.e., the clock frequency, is reduced. Thus, the switching time of the transistor is no longer limited by the drain and source characteristics, but rather significantly depends on the delay associated with signal propagation along the gate electrode 18, i.e., the transistor performance depends, at least in part, on the resistance of the gate electrode 18 in the longitudinal direction of the gate electrode 18, i.e., in the gate width direction. The problem is even more pronounced as the width (i.e., in the longitudinal direction) increases.
Moreover, another problem encountered with device scaling is that some metal suicides, e.g., titanium silicide, do not scale very well. That is, as the length (in the transverse direction) of the gate electrode 18 is reduced, the resistance of the metal silicide regions formed above the gate electrode 18 can increase very rapidly.
The present invention is directed to a method of making a semiconductor device that may minimize or reduce some or all of the aforementioned problems.
The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon and forming a recess in the layer of polysilicon. The method further comprises forming a metal region in the recess and patterning the layer of polysilicon to define a gate stack comprised of the metal region and the layer of polysilicon.